1. Field of the Invention
The present invention relates to feedback systems, and particularly to those circuits useful for implementing a phase locked loop, and more particularly to clock and data recovery circuits.
2. Description of Problem to be Solved and Related Art
Phase locked loops (PLLs) have been known and studied for quite some time. Initially they were very expensive to implement, and found use in only the most technically-demanding and/or cost-insensitive applications. However, as the cost of integrated circuit technology has decreased over the years, and as the performance capability of such integrated circuit technology has increased, today PLLs are extremely inexpensive to implement and are found in wide use in many applications.
A generalized block diagram of a traditional PLL is shown in FIG. 1 which is configured for a clock and data recovery application. The phase locked loop 100 includes a phase/frequency detector 102 which receives the input data signal conveyed on node 112 and the output clock signal of the voltage controlled oscillator (VCO) 110 conveyed on node 124. The phase/frequency detector 102 generates on its output node 116 an error signal which is a function of the phase difference between the input data signal and the VCO clock, and may also include additional circuitry to generate on an output node 114 the reconstructed data, as shown.
A gain block 104, an integrator block 106, and a summer block 108 together form a filter block which low-pass filters the output of the phase/frequency detector 102 to generate a control signal on node 122 which is provided to the voltage controlled oscillator 110 in order to influence the frequency (and hence the phase) of the VCO output signal. The integrator block 106 is often implemented using a charge pump and a loop filter capacitor, as is well known in the art. Such loop filter capacitors are usually required to be very large for the PLL to exhibit acceptable peaking behavior in its frequency response.
In order to appreciate this issue, a brief description of the frequency response of this traditional PLL is warranted. The closed loop transfer function, G(s), of this traditional PLL 100 is set forth in Equation 1:                               G          ⁡                      (            s            )                          =                                                            K                xe2x80x2                                            ω                z                                      ⁢                          (                              s                +                                  ω                  z                                            )                                                          S              2                        +                                                            K                  xe2x80x2                                                  ω                  z                                            ⁢              s                        +                          K              xe2x80x2                                                          (                  Eq          .                      xe2x80x83                    ⁢          1                )            
where Kxe2x80x2 and xcfx89Z are determined by the settings of various PLL parameters. In the traditional PLL 100, the value of xcfx89Z is given by Equation 2.                               ω          z                =                  I          CK                                    (                  Eq          .                      xe2x80x83                    ⁢          2                )            
where I corresponds to the magnitude of the current of the charge pump, C corresponds to the magnitude of the loop filter capacitor, and K corresponds to the gain of the gain block 104. A graph of the frequency response of this closed loop transfer function G(s) is shown in FIG. 2 by curve 130. As shown in this graph, the magnitude of the transfer function is fairly constant at low frequency, and increases slightly for frequencies between xcfx89Z and xcfx89BW (which corresponds to the bandwidth of the closed loop transfer function). As frequency increases above xcfx89BW, the magnitude of the transfer function falls off rapidly. This xe2x80x9cpeakingxe2x80x9d region in the transfer function is labeled as 132.
The magnitude of this peaking is very critical for many applications. For example, the SONET specification limits the acceptable peaking to 0.1 dB. If allowed to exceed this limit, frequency components of input data jitter which fall within this peaking region are actually amplified by the PLL. If several such PLLs are coupled sequentially, the jitter may be amplified to a degree which severely compromises the ability to meet jitter tolerances, or even to correctly recover data.
If we define:                                           ω            BW                                ω            z                          =                  γ                      γ            -            1                                              (                  Eq          .                      xe2x80x83                    ⁢          3                )            
From the SONET specification of 0.1 dB, we arrive at a value of gamma of 1.01. Consequently,                                           ω            BW                                ω            z                          =        101                            (                  Eq          .                      xe2x80x83                    ⁢          4                )            
and                               I          CK                =                              ω            BW                    101                                    (                  Eq          .                      xe2x80x83                    ⁢          5                )            
For the OC48 data rate of the SONET specification, the loop bandwidth must meet the following relationship:
xcfx89BWxe2x89xa62xcfx802 MHzxe2x80x83xe2x80x83(Eq. 6)
The magnitude of the gain factor K is set by the loop bandwidth and the VCO gain, KV, and is typically much less than unity, such as, for example:                                           4            ⁢            π                    50                ≅        0.25                            (                  Eq          .                      xe2x80x83                    ⁢          7                )            
To achieve a reasonably fast charge pump in, for example, 0.25xcexc semiconductor technology, the value of I may be advantageously set to 100 xcexcA. Calculating for the required magnitude of the loop filter capacitor, we arrive at:                               C          ≥                      101            ⁢                          I              K                        ⁢                          (                              1                                  ω                  BW                                            )                                      ⁢                  
                ⁢                              C            ≥                          100              ⁢                                                100                  ⁢                  µA                                0.25                            ⁢                              (                                  1                                      2                    ⁢                    π2MHz                                                  )                                              =                      3.2            ⁢                          xe2x80x83                        ⁢            nF                                              (                  Eq          .                      xe2x80x83                    ⁢          8                )            
This amount of capacitance (3.2 nF) is difficult to integrate onto an integrated circuit without requiring large amounts of die area for the capacitor. For lower data rates, an even greater amount of capacitance is required (e.g., 16 times as much for OC3). For this reason, the loop filter capacitor is usually provided externally. But such an external capacitor adds an additional complexity to board layout, and introduces noise susceptibility on the extremely critical loop filter node within the PLL.
There have been other attempts to reduce the size of the required loop filter capacitor. One such method is described by Bulzachelli in U.S. Pat. No. 5,036,298 in which the input data signal is routed through a variable delay block, whose output is then routed to the phase detector. This results in a zero placed in the loop feedback path that does not appear in the closed loop transfer function, and hence there is no peaking in the closed loop transfer function. The large filter capacitor otherwise required at least partially to achieve acceptably low peaking is not required to be as large. While this is an elegant engineering solution, there are nonetheless difficulties which must be dealt with to implement such a solution requiring a variable delay block. First, it may be difficult to implement a variable delay block having an adequate delay range, especially in multi-rate applications. Additionally, the variable delay block must accurately delay the data signal in spite of the random nature of data transitions in the data signal, where the time between transitions is not necessarily constant. Moreover, the variable delay block represents yet another block of circuitry that must operate at the full data rate, and consequently its power dissipation may not be insignificant, especially when a low power clock and data recovery implementation is desired.
In spite of these previous efforts, and notwithstanding the long history of engineering efforts refining the design of phase locked loops, most PLLs still require either a large external capacitor or require significant additional integrated circuit die area to implement the loop filter capacitor monolithicly. Therefore, additional improvements which can reduce the size of the loop filter capacitor are still greatly desired.
In a feedback system, such as a PLL, the integrating function associated with a loop filter capacitor may be implemented digitally rather than using a traditional integrating capacitor. The area required for such a digital integrating block is easily implemented on the same integrated circuit die as the PLL. There is no need for either an external loop filter capacitor nor for a large loop filter capacitor integrated on the same integrated circuit die as the PLL. Consequently, printed wiring board layout issues are simplified, and at least one dedicated package pin may be eliminated. Other kinds of feedback systems can also benefit by implementing a loop filter capacitor function or other long time constant requirement by digitally synthesizing the integrating capacitor.
In certain embodiments of the invention an analog phase detector may be utilized, whose phase error output signal is converted to a digital signal by an analog-to-digital (A/D) converter. In other embodiments a digital phase detector may be utilized whose phase error output signal is already a digital signal. The digital phase error signal may be digitally xe2x80x9cintegratedxe2x80x9d by a digital integration block including, for example, a digital accumulator block, whose output is then converted back to an analog signal, filtered, optionally combined with a loop feed-forward path signal, and then conveyed as a control voltage to the voltage-controlled oscillator. The equivalent xe2x80x9csizexe2x80x9d of the integrating capacitor function provided by such an arrangement may be varied by increasing or decreasing the number of bits within the digital accumulator block. For example, the number of bits may be changed to adjust a loop filter for different incoming data rates or input frequencies. Consequently, an increasingly larger equivalent capacitor may be implemented by adding additional digital stages, each of which consumes low power and requires a small incremental integrated circuit area.
The required resolution of the digital accumulator output may be less than the number of bits in the accumulator, which allows the lower order bits to be decimated. The high order portion of such a digital accumulator may then be operated at a far lower clock rate than lower order portions, thus reducing power consumption.